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 INTEGRATED CIRCUITS
DATA SHEET
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* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4066B gates Quadruple bilateral switches
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Quadruple bilateral switches
DESCRIPTION The HEF4066B has four independent bilateral analogue switches (transmission gates). Each switch has two input/output terminals (Y/Z) and an active HIGH enable input (E). When E is connected to VDD a low impedance bidirectional path between Y and Z is established (ON condition). When E is connected to VSS the switch is
HEF4066B gates
disabled and a high impedance between Y and Z is established (OFF condition). The HEF4066B is pin compatible with the HEF4016B but exhibits a much lower ON resistance. In addition the ON resistance is relatively constant over the full input signal range.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
PINNING HEF4066BP(N): 14-lead DIL; plastic (SOT27-1) HEF4066BD(F): 14-lead DIL; ceramic (cerdip) (SOT73)) HEF4066BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America APPLICATION INFORMATION An example of application for the HEF4066B is: * Analogue and digital switching E0 to E3 Y0 to Y3 Z0 to Z3 enable inputs input/output terminals input/output terminals
Fig.3 Schematic diagram (one switch).
January 1995
2
Philips Semiconductors
Product specification
Quadruple bilateral switches
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Power dissipation per switch For other RATINGS see Family Specifications DC CHARACTERISTICS Tamb = 25 C VDD V 5 ON resistance 10 15 5 ON resistance 10 15 5 ON resistance `' ON resistance between any two channels OFF state leakage current, any channel OFF En input voltage LOW 10 15 5 10 15 5 10 15 5 10 15 VIL IOZ RON RON RON RON SYMBOL MIN. - - - - - - - - - - - - - - - - - - - - - 2,25 4,50 6,75 TYP. MAX. 350 80 60 115 50 40 120 65 50 25 10 5 2500 245 175 340 160 115 365 200 155 - - - - - nA nA 1V 2V 2V En at VSS P max.
HEF4066B gates
100
mW
CONDITIONS En at VDD Vis = VSS to VDD see Fig.4 En at VDD Vis = VSS see Fig.4 En at VDD Vis = VDD see Fig.4 En at VDD Vis = VSS to VDD see Fig.4
200 nA Iis = 10 A see Fig.9
VDD V
SYMBOL -40
Tamb (c) +25 +85 MAX. 7,5 A 15,0 A 30,0 A 1000 nA
CONDITIONS
MAX. MAX. Quiescent device current Input leakage current at En 5 10 15 15 IIN IDD 1,0 2,0 4,0 - 1,0 2,0 4,0 300
VSS = 0; all valid input combinations; VI = VSS or VDD En at VSS or VDD
January 1995
3
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4066B gates
Fig.4 Test set-up for measuring RON.
En at VDD Iis = 200 A VSS = 0 V
Fig.5 Typical RON as a function of input voltage.
NOTE To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VSS. January 1995 4
Philips Semiconductors
Product specification
Quadruple bilateral switches
AC CHARACTERISTICS (1), (2) VSS = 0 V; Tamb = 25 C; input transition times 20 ns VDD V Propagation delays Vis Vos HIGH to LOW 5 10 15 5 LOW to HIGH Output disable times En Vos HIGH 5 10 15 5 LOW Output enable times En Vos HIGH 5 10 15 5 LOW Distortion, sine-wave response Crosstalk between any two channels Crosstalk; enable input to output OFF-state feed-through ON-state frequency response 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 tPZL tPZH 40 20 15 45 20 15 0,25 0,04 0,04 - 1 - - 50 - - 1 - - 90 - 80 40 30 90 40 30 ns ns ns ns ns ns % % % MHz MHz MHz mV mV mV MHz MHz MHz MHz MHz MHz note 9 note 8 note 7 note 6 note 5 note 4 note 4 10 15 tPLZ tPHZ 80 65 60 80 70 70 160 130 120 160 140 140 ns ns ns ns ns ns note 4 note 4 10 15 tPLH tPHL 10 5 5 10 5 5 20 10 10 20 10 10 ns ns ns ns ns ns note 3 note 3 SYMBOL TYP. MAX.
HEF4066B gates
January 1995
5
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4066B gates
VDD V Dynamic power dissipation per package (P) 5 10 15
TYPICAL FORMULA FOR P (W) 800 fi + (foCL) x VDD 2 3 500 fi + (foCL) x VDD 10 100 fi + (foCL) x VDD
2 2
where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)
Notes 1. Vis is the input voltage at a Y or Z terminal, whichever is assigned as input. 2. Vos is the output voltage at a Y or Z terminal, whichever is assigned as output. 3. RL = 10 k to VSS; CL = 50 pF to VSS; En = VDD; Vis = VDD (square-wave); see Figs 6 and 10. 4. RL = 10 k; CL = 50 pF to VSS; En = VDD (square-wave); Vis = VDD and RL to VSS for tPHZ and tPZH; Vis = VSS and RL to VDD for tPLZ and tPZL; see Figs 6 and 11. 5. RL = 10 k; CL = 15 pF; En = VDD; Vis = 12 VDD(p-p) (sine-wave, symmetrical about 12 VDD); fis = 1 kHz; see Fig.7. 6. RL = 1 k; Vis = 12 VDD(p-p) (sine-wave, symmetrical about 12 VDD); V os (B) 20 log ------------------ = -50 dB; E n (A) = V SS ; E n ( B ) = V DD ; see Fig. 8. V is ( A ) 7. RL = 10 k to VSS; CL = 15 pF to VSS; En = VDD (square-wave); crosstalk is Vos (peak value); see Fig.6. 8. RL = 1 k; CL = 5 pF; En = VSS; Vis = 12 VDD(p-p) (sine-wave, symmetrical about 12 VDD); V os 20 log -------- = -50 dB; see Fig. 7. V is 9. RL = 1 k; CL = 5 pF; En = VDD; Vis = 12 VDD(p-p) (sine-wave, symmetrical about 12 VDD); V os 20 log -------- = -3 dB; see Fig. 7. V is
Fig.6
Fig.7
January 1995
6
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4066B gates
Fig.8
Fig.9
January 1995
7
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4066B gates
Fig.10 Waveforms showing propagation delays from Vis to Vos.
(1) Vis at VDD (2) Vis at VSS.
Fig.11 Waveforms showing output disable and enable times.
January 1995
8


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